Simplex ARQ system

ABSTRACT

An improved simplex ARQ system for data transmission circuits using a short wave circuit is provided. A block of characters is sent from a master station to a slave station and if an error occurs during the transmission, said block of characters is automatically re-transmitted, thus clean output without an error is obtained on a printer in a receiving or slave station. The length of said block is changed according to the instantaneous quality of the short wave circuit, and thus the actual transmission speed is considerably increased.

United States Patent Shimizu et al.

[ Apr. 15, 1975 [5 SIMPLEX ARQ SYSTEM 3,593,281 7/1971 Van Duuren et al.178/23 A [75] Inventors: Otoomi Shimizu, Saitama-ken;

:htoshl Koyano Tokyo both Of Primary Examiner-Thomas A. Robinson apanAttorney, Agent, or Firm-Paul & Paul [73] Assignee: Oki ElectricIndustry Co., Ltd., Tokyo, Japan [22] Filed: Dec. 5, 1973 57 BS [2|]Appl. No.: 421,947

An improved simplex ARQ system for data transmission circuits using ashort wave circuit is provided. A [30] Fme'gn Appl'catm Pnomy Data blockof characters is sent from a master station to a DEC. '2, i972Japan........... lave station and an error occurs during the trans.

mission, said block of characters is automatically re- Cl 178/23340/1461 AL transmitted, thus clean output without an error is 0b- [5llllt- 1 tained on a printer in a receiving or lave station The Searchl73/23 2 A, length of said block is changed according to the inl78/DIG.l2; 340/ 46 I 1 stantaneous quality of the short wave circuit. and thus179/15 325/38 33 A, 33 B the actual transmission speed is considerablyincreased. [56] References Cited UNITED STATES PATENTS 5 Claims, 11Drawing Figures 3,506,96! 4/[970 Abramson et al.. 340/146,! AL

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sum 5 mg 9 DATA READ 75 SIMPLEX ARQ SYSTEM The present invention relatesto an error correcting system in printing telegraph and. in particular.relates to an error control system in short wave telecommunicationcircuits whose quality is generally unstable due to fading. interferenceand unstable transmission path.

There are many known error correcting systems. among which the ARQsystem. which stands for Automatic Repeat Request. is a typical. gooderror correcting system. ARQ was originally recommended by the CCIR(Comite Consultatif International des Radio Communication) of the ITU(International Telecommunication Union) as Recommendation CCIR 47b formessage transmission using a short wave circuit. ARQ provides a cleanoutput which has no errors on a receiving printer. in spite of thepresence of transmission errors. by automatically correcting thoseerrors. and is suitable for a printing telegraphy system using a shortwave circuit. The quality of short wave circuits is not good and isabout It) It) in character error rate due to fading. interference etc..while a printing telegraphy system ordinarily requires at least IIIerror rate. Accordingly. ARQ provides an excellent means for correctingerrors in printing telegraphy caused by unstable short wave circuit.

The prior ARO system converts. at a transmitting or master station. afive element start-stop code to a seven element code by removing thestart and stop elements. Four elements of the seven element code aremarks or I and three elements are spaces or O. The transmitting stationsends said seven element code for a block. which usually consists ofthree characters each of which has said seven elements. and then thetransmitting station waits for an acknowledgement from a receivingstation. At a receiving or slave station. a received block is tested todetermine if each of the seven element characters in the block has fourmark elements and three space elements. When the signal is receivedwithout an error. the signal is again converted from a seven elementcode to a five element code by adding start and stop elements and issent to a receiving terminal or printer. At the same time the receivingstation transmits an acknowledgement signal CSI or CS2 to thetransmitting station. The alternative transmission of CS1 and CS2between each block received by the receiving station means that thesignal is being received without any error.

However. if any error occurs due to fading or interference in atransmission circuit. a mark element changes to a space element. or viceversa. and destroys the condition of four marks and three spaces at thereceiving station. When the receiving station recognizes an error. itstops sending the received signal to the receiving printer and returnsdouble CSI or double CS2 to the transmitting station. In receiving saiddouble CS1 or double CS2. the transmitting station stops sending aseries of messages and re-transmits the last transmitted message blockwhich consists of three characters.

At the receiving station if the re-transmitted block is received withouterror it is passed to the receiving printer. while if an error is againdetected the double CSl or double CS2 procedure is repeated until theblock is received without error and is passed to the receiving printer.Thus a clean output without any error is obtained on the receivingprinter.

Accordingly. in the above described prior ARO sys' tent. thetransmitting station alternately sends a message block and waits for theCS1 or CS2 acknowledgement. The ratio of the sending duration to thewaiting duration depends upon the propagation time of the signal betweenthe two stations. switching time for the alternate sending and receivingoperation and control time for processing the control signal such as CSIor CS2 etc. Said ratio is l l. or the waiting duration exceeds thesending duration. Accordingly the time efficiency of the prior AROsystem could not be more than 0.5. even if the transmission circuit isideal and no transmission error occurs.

A disadvantage of the prior ARQ system is that the circuit efficiency issmall due to frequent switching of sending and receiving operations andlong waiting periods.

The other disadvantage of the prior ARO system is that actualcommunication speed is low. due to said small efficiency. when comparedto the original transmission speed in the propagation circuit.

Accordingly. an object of the present invention is to provide animproved simplex ARQ system which overcomes the above-mentioneddrawbacks.

Another object of the present invention is to provide an improvedsimples ARO system whose efficiency and communication speed aresatisfactory.

A further object of the present invention is to provide an improvedsimplex ARQ system which enables the effective use of the small numberof short wave frequencies and shortens the communication time.

According to the present ARQ system. the number of characters in a blockis variable. and the length of a block is an integer multiple of a basicblock. for instance an odd multiple of the basic length. and the lengthof a block is controlled according to the instantaneous quality of thetransmission circuit. Thus the transmission circuit is utilizedeffectively and the information or message is transmitted with highspeed and high accuracy.

Further features and advantages ofthe present invention will be apparentfrom the ensuing description with reference to the accompanying drawingsto which. however. the scope of the invention is in no way limited.

FIG. 1 shows curves concerning the relationship between the number ofcharacters in a block and the transmission efficiency.

FIG. 2 shows a curve concerning the relationship between the number ofcharacters in a block and the transmission speed:

FIG. 3 shows a brief block diagram of a short wave communication systemutilizing simplex ARO terminal equipment according to the presentinvention;

FIG. 4 shows an explanatory brief time chart of the operation of asimplex ARQ communication system according to the present invention;

FIG. 5 is a brief block diagram of a simplex ARQ ter minal equipmentaccording to the present invention;

FIG. 6 is a detailed block diagram of a transmission memory 13. a codetransmission circuit I4 and a transmission control IS in FIG. 5;

FIG. 7 shows a general flow chart of the transmitting operation of asimplex ARQ system according to the present invention;

FIG. 8 shows an explanatory detailed time sequence of the operation of asimplex ARQ system according to the present invention;

FlG. 9 is a detailed block diagram of a receiving control 16. a codereceiving circuit 18. a code detection circuit and a receiving memory 20in FIG.

FIG. shows a general flow chart of the receiving operation of a simplexARQ system according to the present invention;

FIG. ll shows a block diagram of a mode switching circuit of a simplexARQ system according to the pres ent invention.

At first. the influence of the number of characters in a block to thecommunication efficiency is mathematically analyzedv In the followinganalysis. the ratio of the time Z/N in which one character istransmitted with constant speed without an acknowledgement and the time1' in which one character is transmitted with an acknowledgement foreach block will be explained. For explanatory purposes it is assumedthat the waiting time between blocks in the latter part ofthe aboveratio is the period required for the transmission of the threecharacters.

a. The number of blocks to be transmitted is N/n; wherein N is thenumber of characters to be transmit led and u is the number ofcharacters in a block.

b. The time for transmission of all blocks neglecting retransmission is(u 3 )1' N/n; where r is the time required for transmission of acharacter.

c. The time for transmission of all blocks including repetition orrc-transmission time is .'\'/i|tn 3)T(l +Q+ (2 .l where O is the blockerror rate. in the second parenthesis above. I relates to the case whereno error occurred. 0 relates to the case where an error occurred once. 0relates to the case where an error occurred twice. etc.

d. The relationship between the block error rate Q and the charactererror rate is Q Pl n l l where an effective number of characters in ablock is assumed to be (u 1). including the transmission of a controlcharacter. and errors occur at random.

e. Accordingly. the period Z that is required for transmission of Ncharacters by blocks having n characters. neglecting higher terms thanQ. is

f. Therefore. the ratio of the period Z/N for one character transmissionwith an acknowledgement. to the period T for one character transmissionwithout an acknowledgement is:

HO. I shows the curve of above equation. in which the horizontal axisrelates to the number of characters n in a block and the vertical axisshows the value of Z/Nr. and the curves u. h and r" relate to charactererror rate it)". it and 10". respectively.

From FIG. 1. it will be clearly understood that the optimum number ofcharacters in a block is 3 or 4 characters when error rate is l0". l5 orl6 characters when error rate is l0'. and about lOt) characters whenerror rate is l()''.

FIG. 2 shows the relationship between the number of characters in ablock in the horizontal axis and communication speed (characters perminute) in the vertical axis. The waiting period between eachtransmission in ltl FIG. 2 equals the period for transmission of threecharacters and the transmission time for one character is lUtl mS. Forinstance. if a block length is three characters long the communicationspeed is 300 characters per minute. however. the communication speedcannot exceed 600 characters per minute whatever the length of the blockmay be. Further. the block length of about 20 characters is preferablein view of the block length and communication speed.

The quality of a short wave circuit is on the order of HF' ltl incharacter error rate and. therefore. the block length according to thepresent simplex ARO system is changed automatically or manuallyaccording to the instantaneous quality of a transmission circuit.Preferably. the block length is changed from three characters to fifteencharacters. or vice versa.

HO. 3 shows a brief block diagram of a short wave communication systemutilizing simplex ARQ terminal equipment according to the presentinvention. In FIG. 3. the station A is a master which controls the wholecommunication system and the station B is a slave. A message istransmitted from the master station to the slave station while anacknowledgement signal is transmitted in the opposite direction. First atransmission circuit is provided between stations A and B by selectivecall and then the station A reads an input message from an input-outputdevice I. The code of said message is. for instance. a five unitstart-stop code and the communication speed is Bv An ARO terminal 2converts the five unit start-stop code to an error detecting code like athree-out-of-seven-elemeats-code. and makes a block consisting of threeor fifteen characters. Each block is sequentially transmitted to thestation B through a transmitter 3 and an antenna 5. The waiting timebetween each block equals three-characters in length. It should be notedhere that communications speed in a short wave circuit should be atleast twice as fast as in a line circuit. since in the former thetransmission is interrupted every three characters. Accordingly if theline speed is 50 bits/sec. the communication speed in a radio channel isat least ltll) bits/sec. The station B receives the message from stationA through an antenna 5' and a receiver 4'. An ARQ equipment 2 of stationB tests if the received message is correct. ARQ 2' deems the messagecorrect if each seven elements character is composed of four marks andthree spaces. The correct message is re-converted from a seven ele mentcode to a five element start-stop code and sent to an input-outputdevice 1' like a printer. The station B returns an acknowledgementsignal CS1 or CS2 consisting ofone character length to the station Athrough a transmitter 33' and an antenna 5'. lfthe message is receivedcorrectly. CS1 and CS2 are alternately transmitted. while double CSl orCS2 is transmitted if the received message is wrong. The station Areceives said transmitted signals through an antenna 5 and a receiver 4to the ARQ equipment 2. which transmits a next block if the precedingblock was correct and acknowledgement signals CS1 and CS2 are receivedalternately. or retransmits the preceding block if CS] or CS2 isreceived twice successively. As is apparent from above explanation. themaster station transmits a message and receives an acknowledgement.while the slave station receives a message and transmits anacknowlcdgement. thus a clean output is obtained on a printer at areceiving station.

FIG. 4 shows an explanatory brief time chart of the operation of theARC) communication system. In FIG. 4. the operational mode of the ARQ isat first mode I in which a block is of length three characters. then themode is changed to mode 2 in which a block length is l5 charactersaccording to the present invention. In FIG. 4, a message is transmittedby either mode I in which the block length is three characters in lengthand the waiting time is also three characters in length. or mode 2 inwhich the block length is I5 characters in length and the waiting timeis three characters in length. A is a master station and B is a slavestation and a message is transmitted from station A to station B whilean acknowledgement signal is transmitted from station B to station A.When a circuit between stations A and B is provided by. for instance.selective call. the system is initiated in mode I, and the station Bsends a control signal CS1 at time IT. which is received by the stationA at time IR.

Upon receiving a signal CSI at time 1R. the station A sends a messageblock (BLK consisting of three characters at time I'T. which is receivedby the station B at time I'R and if BLKl is received correctly thestation B sends an acknowledgement or control signal CS2 at time 2T.which is received by the station A at time 2R. However. if BLKI isreceived wrong by the station B. the station B sends CSI instead of CS2.since the preceding control signal was CS1. thus double CS] would bereceived by the station A. The above cycle is repeated and the station Asends BLKZ at time Z'T and BLKI at time 3T and the station B sends CSIat time 3T and CS2 at time 4T.

At this time. suppose that a switching command which changes a blocklength from three characters in length to fifteen characters length isapplied to the system. Then. the station A sends a signal a at time 4'T.which is received by the station B at time 4'R. The signal 01 consistsof three characters and its meaning is to command preparation for modeswitching in the station B. When the station B recognizes the signal a.the station B sends control signal CS3 instead of (S1 at time ST. andCS3 is received by the station A at time SR. Next. the station A sends asignal B at time ST. which is received by the station B at time 5'R. Thesignal [3 also consists of three characters and its meaning is tocommand actual mode switching in the station B. When the station Brecognizes the signal [3. the station B sends a control signal CSI attime 6T. which is received by the station A at time 6R. Thus the mode oftwo stations A and B is changed from mode 1 to mode 2. Next. the stationA sends a block BLKI consisting of IS characters at time 6'T. which isreceived by the station B at time 6R. and a similar cycle is repeatedand y the station A sends BLKII at time 7'T and BLTI at time 8'T. whilethe station B sends acknowledgement signals CS2 at time 7T and CS] attime ST.

The signals a and B consist of three characters if the switching commandappears under mode 1. while they consist of fifteen characters if theswitching command appears under mode 2.

Suppose that the control signal CSI sent by the sta tion B at time 6Twas not received correctly by the station A. In this case though thestation B changes to mode 2 while the station A remains in mode 1, thesystem according to the present invention works well. This is becausethe period that the station B in mode 2 returns CSI, coincides with aperiod that the station A in mode I awaits CS1. thus the station A candefinitely receive CSl sooner or later before several blockstransmission. and change to mode 2.

FIG. 5 shows a brief block diagram of the simplex ARQ terminal equipment2 or 2' in FIG. 3. In FIG. 5. reference number II shows a standardfrequency oscillator (OSC) which generates several kinds of clock ortiming pulses. I2 is a mode switching circuit which changes theoperation mode of the ARO system from mode 1 to mode 2 or vice versathereby changing the number of characters in a block. 13 is atransmission memory (TMEM) which has a register for each operation modefor re-transmission. H is a code transmission circuit (T) which receivesa live element start-stop code. converts it to a seven element errordetecting code and sends it to a transmitter (TX )3 in FIG. 3. I5 is atransmission control (T CONT) which controls the transmission of amessage or control signal with a pre' determined procedure during atransmission period obtained by the division of clock pulses from theoscillator (OSC)ll. I6 is a receiving control (R CONT) which controlsthe received message and control or acknowledgement signal with apredetermined procedure during a receiving period obtained by thedivision of clock pulses from the oscillator (OSC )l I. I7 is atransmitter and receiver control (T/R CONT) which controls the operationof a transmitter (TX)3 and a re ceiver (RSH in FIG. 3. I8 is a codereceiving circuit (R) which receives signals from the receiver (RX )4.I9 is a code detection circuit (DET) which receives signals from thecode receiving circuit (R118 and tests if an error has occurred in theradio transmission circuit. 20 is a receiving memory (R MEM whichtemporarily stores the received signal and passes it to an inputoutputdevice like a printer.

The operation of FIG. 5 is briefly explained here. but it will bedescribed in detail later with reference to FIGS. 6 through 10. Supposethat the ARO equipment in FIG. 5 is the master station A (FIG. 3) and itreceives a control signal CSI at time IR (FIG. 4). The signal CS1 passesthrough the code receiving circuit (R)I8 and is detected by the codedetection circuit (DET)l9. The receiving control (R CONT)"; memorizesthe fact that the station A received the signal CS1. At this time thetransmission control (T CONT)]4 is at a state of step 4 (laterdescribed) which is a state of waiting for a control or acknowledgementsignal. Since CS1 shows that no error occurred. the ARQ reads thesucceeding. three characters. switches ON the transmitter (TX)3 throughthe transmitter and receiver control (T/R CONT)I7. drives thetransmission memory (T MEM )I3 and the code transmission circuit (T)I4.and transmits the three characters at time l'T (FIG. 4).

Next. the operation of a slave station B is briefly explained. The AROin the station B receives said three characters at time l'R which isduring the receiving period indicated by the receiving control (RCONT)I6. The received three characters are tested by the code detectioncircuit (DET)l9 to determine if an error occurred or not. If all threecharacters were received correctly. a counter in the code detectioncircuit (DET)l9 provides an output signal to the transmission control (TCONTHS, which switches ON the transmitter (TX)3 through the transmitterand receiver control (T/R CONT) I7 and sends a signal CS2 through thecode transmission circuit (T)l4 at time 2T. The received threecharacters are. of course. sent to an input-output device through thereceiving memory (R MEM )20.

FIG. 6 shows a detailed block diagram of the transmission memory (TMEMll3. the code transmission circuit (TH-l. and the transmissioncontrol (T CONTJIS of FIG. 5. In FIG. 6. input characters go through ANDcircuit 50 or to flip-flops 52-l 52-3 or flip-flops 53-] 5345. accordingto the mode at that time. and the characters stored in said flip-flopsgo to the code transmission circuit (Tll-I through AND circuit 54 or 55.and OR circuit 56. Each flip-flop 52-l 52-3 or 53-] 53-l5 functions tostore one character respectively. In the code transinission circuit(TH-I. a transmission register 63 recei\ es a message or control signalCS1. CS2 or CS3 through OR circuit 62 and AND circuit 57-60 according tothe presence of the gate signal DATA. CS I. CS2 or CS3 for AND circuit57-60. A control signal generator 6] generates the pattern of controlsignal CS1. CS2 and CS3 and supplies them to AND circuit 58-60. Thecontent of said register 63 is shifted bit by bit by a shift pulse t3sent through line 67. and is composed into an error detecting codethrough a check element generator 64 and OR circuit 65. the output ofwhich is sent to a transmitter (TX) through a level converter 66.

A step counter 68 determines the state or step of the ARQ equipment toone of the states 0 6. and supplies an output signal at one of sixoutput lines. The operation concerning the transmission in each state isex plained with reference to the state diagram of FIG. 7 and the timechart in FIG. 8. In FIG. 8. (A shows characters to be transmitted. (B).(C). (D) and (E) show timing pulses II. 12. (3 and 14 respectively. and(F) sho s the state or step of the transmission operation for eachtiming.

In step 0. the output signal appears on 0 output line. but ARO equipmentdoes not work during step 0. Suppose that a selective call was made or atransmitter (T\') was switched ON at time to of FIG. 8(F). then the stepchanges to step 1 (reference number 31 in FIG. 7 During step I. anoutput signal appears on output line I of the step counter 68. and saidsignal is applied to AND circuit 69. When timing pulse II appears (FIG.8(8)). said AND circuit 69 provides signal TX ON. which switches ON atransmitter (TX). and the step changes to the step 2 since a signal fromAND circuit 69 is applied to the step counter 68 through OR circuit 77and AND circuit 78 (reference number 32 and 33 in FIG. 7).

During step 2. an output signal appears on output line 2 of the stepcounter 68, which is applied to AND circuits 70. 7] and 72. If thestation is a master (M). AND circuit 70 applies its output signal to ashift pulse generator 80 through OR circuit 79 at a timing (2 (34 inFIG. 7 and FIG. 8(C) Said shift pulse generator supplies a shift pulseto the transmission memory (T MEMIIS and one character in said memory [3is sent to the code transmission circuit (T)I4 (35 in FIG. 7 Uponreceipt of said character the code transmission circuit (T)l4 convertsthe five element start-stop code to a seven element error detectingcode. which is shifted and transmitted bit by bit in series by timingpulse I3 (36 and 37 in FIG. 7). The operation of reference number 36 and37 in FIG. 7 is repeated until one character is completely sent out (38in FIG. 7). An output of AND circuit 70 is also applied to a counter 81.which counts how many characters in a block have been sent out.

When all characters in a block (three characters in mode I or 15characters in mode 2) have been sent out. AND circuit 82 or 83 applies asignal through OR circuit 84. AND circuit 7]. OR circuit 77 and ANDcircuit 78 to the step counter 68. the content of which. then. changesto step 3 (39 in FIG. 7).

If the station is a slave (5) during step 2. AND circuit 72 provides asignal to the shift pulse generator 80. howev er. since one character isenough in a slave station to send. a signal is also applied to the stepcounter 68 promptly through AND circuit 72. OR circuit 77 and ANDcircuit 78 and causes the change of the step to step 3.

During step 3. an output signal appears on output line 3 of the stepcounter 68. said signal is applied to AND circuit 73. which provides asignal to a counter 92 each time timing pulse t3 (FIG. 8(D)) appears.When the content of the counter 92 reaches a predetermined value. anoutput signal from the counter 92 is provided in order to switch OFF atransmitter (TX). (40 in FIG. 7) and the step changes to step 4.

Step 4 is a period of waiting for the result of the test of thepreceding transmitted characters. The result is an acknowledgement CS]or CS2 sent by the receiving stations. and is definitely obtained duringstep 4 at timing (4 (4] in FIG. 7). Said result is applied to thereceiving control (R CONT) I6 for judgement.

During step 5. a signal from output line 5 of the step counter 68 isapplied to AND circuits and 76. When the station is a master during step5. AND circuit 75 provides an output signal on the conditions thatsignal OK is provided (42 in FIG. 7). Signal OK appears in case theresult in step 4 is correct. The output (DATA READ of AND circuit 75causes the input of succeed ing characters from input-output device toARO (43 in FIG. 7) and the reset of a re-transmission counter 89 (44 inFIG. 7) through OR circuit 88. Said output of AND circuit 75 also causesthe jump of the step to step I through OR circuit 87. However. iftheresult in step 4 shows wrong. no signal appears at output of AND circuit75. and thus. the step changes automatically to step 6.

On the other hand. when the station is a slave (5) during step 5. ANDcircuit 76 provides an output signal on the condition that signal OK isprovided. Signal OK appears when a block of characters are correctlyreceived. The output of AND circuit 76 causes the transfer of receivedcharacters from ARQ to the inputoutput device through line 93. andtriggers a selection circuit 90. which selects an acknowledgement signalCSI or CS2 alternatively. The output of the circuit 90 CSI and CS2 areapplied to AND circuit 58 and 59. respectively. Further. the output ofAND circuit 78 causes the reset to zero of the re-transmission counter89 through OR circuit 88. and the jump of the step to step 1 through ORcircuit 87. However. if the signal OK does not appear. no output signalappears at output of AND circuit 76. and thus. the step changes automatically to step 6.

During step 6. an output signal on line 5 of the step counter 68 isapplied to the re-transmission counter 89 causing the up-count thereof.and the AND circuits and 86. If the content of the re-transmissioncounter 89 has reached a predetermined value, (Y in 45 in FIG. 7 thecounter 89 provides a signal to AND circuit 86, causing the appearanceof ALARM signal and the jump of the step counter 68 to step 0. This isthe case when the transmission circuit is extremely poor and thecommunication between the two stations cannot be continued. However. ifthe content of the re-transmission counter 89 has not reached thepredetermined value (N in 45 in FIG. 7). and inverter 91 applies asignal to AND circuit 85. which causes the jump of the step counter 68to step 1 through OR circuit 87. Thus the communication is continued.

FIG. 9 shows a detailed block diagram of the rccciv ing control (RCONT)16. the code receiving circuit (R )18. the code detection circuit(DTE119 and the receiving memory (R MEM )20 in FIG. 5. which concern thereceiving operation of a simples ARO equipment.

In FIG. 9. a shift register 101 receives characters from the receiver(RX The content of the register 101 is shifted. bit by bit. according tothe applied shift pulse through line 103. The output of the register 101is applied to the receiving memory (R MEM )20 and a code detectioncircuit 111. A test circuit 102 also receives characters from thereceiver (RX) and tests if each character is correctly received. Thecircuit 102 recognizes the received character correctly when seven elements of the character consist of four marks and three spaces. Thereceiving memory (R MEM )20 comprises AND circuits 10-1. 105. 108 and109. flip-flops 106-1 1063 and 107-1 107-15. and OR circuit 110. Theconfiguration of the receiving memory (R MEM )20 is similar to thatofthe transmission memory (T MEM)13 in FIG. 6.

FIG. 10 shows an operational flow chart of FIG. 9. The receiving control(R CONT)16 works each time a character is received (FIG. 8(G and theoperation of it is triggered by timing 15 in FIG. 8(H).

A step counter (STCl12-1 in the receiving control (R CONT 16 determinesthe receiving operation of ARQ equipment.

Step is a period that the receiving control (R CONT] 16 does notoperate. A timing pulse 15 during step 0 changes the step to step 1through AND circuit 126 (47 in FIG. 10 and FIG. 8(lll.

During step 1. a signal is applied to the first gates of AND circuits127 and 128 from the step counter 124.

Suppose that the station is a master (M I. AND circuit 127 provides acontrol signal to the code detection circuit 111 during the time asignal 133 appears. The signal 133 means that it is a receiving periodofthe master station. Then the code detection circuit 111 tests thecharacter supplied from the shift register (SR J10]. and if thecharacter is control signal CS1. CS2 or CS3. an output signal CS1. CS2or CS3. is provided through flip-flop 112, 113 or 114, respectively. Atthe same time. a circuit consisting of AND circuits 116 and 117, ORcircuit 118 and flip-flop 115 tests if signals CS1 and CS2 occuralternatively and provides a signal OK on the same condition.

On the other hand. suppose that the station is a slave AND circuit 128provides a signal to the code detection circuit 111, AND circuit 129 anda shift pulse generator (SG )131 during the time signal 132 meaning areceiving period of the slave station being applied to said AND circuit.The shift pulse generator (SGll31 causes a shift ofthe receivedcharacters in the receiving memory (R MEM )20. AND circuit 129 applies asignal to a counter (C)119 when the received character is not a controlcharacter and a signal OK meaning that the character was receivedcorrectly from the test circuit 102 (48 in FIG. The counter 119 countshow many characters have been received (49 in FIG. 10). When the contentof the counter 119 reaches a predetermined value. namely the number ofcharacters in a block. three or fifteen. a signal 123 meaning that allcharacters in a block have been received correctly is provided throughAND circuits and 121 and OR circuit 122.

During the steps 2 5. in rare operation cases such as the reception of aselection call. the count that how many control signals have beenreceived without a break. etc. are performed. The operations in steps 25 are. however. not essential for the present invention and are notdescribed in detail.

FIG. 11 shows a block diagram of a mode switching circuit (MODEHZ inFIG. 5.

In FIG. 11. a flip-flop (FF1)157 which receives a manual switchingcommand (MANUAL) and an automatic switching command (AUT) through ORcircuit 154. triggers a mode switching operation by providing a signalon its output line N. When the mode switching operation is notcommanded. AND circuit provides an output signal on the condition thatthe step of the transmission control (T CONT) in FIG. 6 is step 5. thestation is a master (M) and the acknowledgement signal shows thetransmission was right (OK). The output signal of the AND circuit 150commands the read ing of the succeeding characters through line 162. andthe transmitting of characters through OR circuit and a flip-flop(FFOllSb and line 163.

When the mode switching operation is commanded. the flip-flop (FFI )157turns ON and AND circuit 151 provides an output signal to a flip-flop(FFZ I158 turning ON said flip-flop 158 at step 5. The Ilipd'lop (FFZH58 provides a signal through line 164 command-- ing the transmission ofsignal a in FIG. 4. The signal a is actually transmitted during nextstep 1. When the station receives a signal CS3 during the time said Ilipflop (FF2)158 is ON. a flip-flop (FF3H65 is turned ON. and a signalcommanding transmission of signal (3 in FIG. 4 is provided through line165. Further. on rcceiv s ing the signal CS1 during the time theflip-flop (FF3l159 is ON. AND circuit 153 provides an output signal.which triggers the switching of a flip-flop (FF-H160 and switches theoperational mode from mode I to mode 2 or vice versa by prmiding signalsMODE 1 on line 167 or MODE 2 on line 166. The signals MODE 1 and MODE 2are supplied to many locations of the ARO equipment. such as ANDcircuits 50 and 5]. AND circuits 82 and 83 in FIG. 6. and AND circuits104 and 105 and AND circuits 120 and 121 in FIG. 9. defining theoperational mode. After the completion of the mode switching operation.the flip-flop (FFOJ1S6 turns ON and the normal operation in a new modeis preformed.

If a switch (S) in FIG. 11 is closed. the mode switching operation isautomatically performed according to the quality of the transmissioncircuit. In FIG. 11. a counter (COU)161 counts an output signal of ANDcircuit 150. The counter 161 is reset to zero by the signal in step 6.Therefore the content of the counter 161 indicates the number ofcharacters received correctly without a break. When the content of thecounter 161 reaches a predetermined value. a signal is applied to theflip-flop (FFO)I57 from the counter 161 through the switch (S) and ORcircuit 154, and the mode is changed from mode 2 15 characters) to mode1 (three characters).

It should be understood that many modifications of FIG. ll may bepossible to those skilled in the art. For instance. full automaticswitching including the switching from mode I to mode 2 and mode 2 tomode I in both master and slave stations according to the quality of thetransmission circuit is possible. Further. if the ratio of characters ina block of mode 1 to that of mode 2 is an odd integer. the ARQ equipmentcan be simple in design.

According to the present invention. the transmission efficiency is. forinstance. increased 67 percent assuming that the characters in a blockare three characters in mode 1 and fifteen characters in mode 2. fromFIG. 2.

As is apparent from the above explanation. the ARC system with variablelength blocks used in a short wave circuit provides effective use of thefrequency band and transmission time. Since the short \va\e band isrecently very crowded. the effect ofthe present invention is extremelybeneficial.

What is claimed is:

l. A method for transmitting digital data in a simplex ARO communicationsystem consisting ofa master and a slave station comprising the steps oftransmitting a block of characters from the master station to the slavestation. transmitting a control signal from the slave station to themaster station indicating if said block of characters has beentransmitted correctly. retransmitting said block of characters in thecase where said control signal indicates the preceding block ofCharacters was transmitted incorrectly. characterized in that the numberof characters in said block is variable in direct correspondence withinstantaneous transmission quality.

2. A method according to claim I. wherein said number of characters in ablock is an integer multiple as large as a predetermined integer.

3. A method according to claim I. wherein said number ofcharacters in ablock is an odd multiple of a basic length.

4. A method according to claim I. wherein said numher ofcharacters in ablock is changed according to the quality of the transmission circuit.

5. A simples ARQ system comprising at least a transmission memory (TMEM) having two series of memo ries for temporarily storing a block ofcharacters to be transmitted. a receiving memory (R MEM) having twoseries of memories for temporarily storing a block of receivedcharacters. a transmission control (T CONT) for controlling theoperation of said transmission memory (T MEM a receiving control (RCONT) for controlling the operation of said receiving memory (R MEM).and a mode switching circuit (MODE) for at least switching said seriesof memories in the transmis sion memory (T MEM) and the receiving memory(R MEM

1. A method for transmitting digital data in a simplex ARQ communicationsystem consisting of a master and a slave station comprising the stepsof transmitting a block of characters from the master station to theslave station, transmitting a control signal from the slave station tothe master station indicating if said block of characters has beentransmitted correctly, retransmitting said block of characters in thecase where said control signal indicates the preceding block ofcharacters was transmitted incorrectly, characterized in that the numberof characters in said block is variable in direct correspondence withinstantaneous transmission quality.
 2. A method according to claim 1,wherein said number of characters in a block is an integer multiple aslarge as a predetermined integer.
 3. A method according to claim 1,wherein said number of characters in a block is an odd multiple of abasic length.
 4. A method according to claim 1, wherein said number ofcharacters in a block is changed according to the quality of thetransmission circuit.
 5. A simplex ARQ system comprising at least atransmission memory (T MEM) having two series of memories fortemporarily storing a block of characters to be transmitted, a receivingmemory (R MEM) having two series of memories for temporarily storing ablock of received characters, a transmission control (T CONT) forcontrolling the operation of said transmission memory (T MEM), areceiving control (R CONT) for controlling the operation of saidreceiving memory (R MEM), and a mode switching circuit (MODE) for atleast switching said series of memories in the transmission memory (TMEM) and the receiving memory (R MEM).